Hey everyone, I’m more of an FPGA guy than an ASIC guy.

We’re building openTPU, an open-source AI accelerator with the whole stack in one repo: architecture, RTL, ISA, simulator, compiler, and host tools. It already runs some pretty respectable models like Qwen3.5 on a Kintex-7 PCIe card.

With help from the community, we’ve now routed our first design using Nangate45. I’d love to get some ASIC eyes on it, especially on the floorplan, timing constraints, and anything we might be overlooking as we move from FPGA to ASIC.

Feedback, contributions, and a good technical roast are all welcome. If you love this stuff, come have fun with us.

https://github.com/FeSens/openTPU

Italy was one of the first countries to implement the new EU directive that makes companies having to reveal a salary range for the positions they post.

I am baffled by how low these companies put their wages.

Less than 5 YoE? Expect a salary in the 30k to 39k range. Want 50k or more? Only with 7+ years.

And this is not for small villages in the middle of nowhere, it is in cities like Milan where the cost of living is crazy expensive. Moreover, if the company has offices in multiple locations they don't adjust their compensation to reflect the cost of living differences. It is a fucking joke, it is like they are lowballing as much as they can to see who accepts it.

I have been trying to change jobs but honestly feel more and more discouraged to apply to Italy, and it also makes me angry how people can accept such low conditions. Please remember that by accepting such a low wage you are not doing a favour to anyone but these greedy companies. It worsens the market for everyone.

Hi everyone,
I’ve completed all 4 interview rounds for a Google India Verification Engineer role, with positive feedback. HR then asked for some additional information, and it’s been around a week.

HR now says “the team is reviewing my feedback and will make a final decision regarding my level and next steps. They also clarified that the decision depends solely on my candidacy, not other candidates.”

Has anyone experienced this? What does this stage mean, and how long did it take to get the final decision?

Not sure if this belongs here as I posted on r/ece

Hey everyone! So I am planning on heading into my Accelerated Bachelors Master program. I won't start until Fall 2027 and I've been told it would reduce my time significantly at my university even if I pursue a PhD. So what I want to do is design the hardware what I am looking into and actually am good at is Digital Circuit design in VLSI, ASIC/FPGA, CMOS, and possibly Computer Arch if I can fit it in, I highly doubt I can. Point is I am already an undergrad researcher and in a fellowship. I am actually not doing research in my field but it is consider a material that translate to EE. I do not want to go into my masters and take classes that I may dislike. So far I like what I am learning but I want to make sure this is where I want to be.

What is the day to day life like?

Will I have time for my family and friends? How about hobbies?

How will I know if this is for me without getting exposure or do I actually need exposure?

I do not want to regret my decision. How did you know this was the right career path for you?

If given the stipend to continue research and pursue a masters or PhD which should I aim for?

Are there any project I can do currently?

Lastly, of course how is the salary in today's economy and is employability high for this type of work?

Hello,

I was recently in an interview wherein I was asked simple questions about poles and zeros in a single transistor circuit, and bode plots and two stage op amp design. I know these topics, but as soon as a new question comes up, I mess it up. Where can I get practice questions to help me prepare better ? I have solved Razavi’s exercises, but I can’t apply myself on the interview. Are there any other helpful materials?Any suggestions are welcome.

Thanks !

Hi everyone, I can refer candidates for the open roles listed in the image. DM me if you match the requirements.

Roles:

Electronics Hardware Engineer (2-5 yrs, Bengaluru)

Hardware Architect Electronics (2-5 yrs, Coimbatore)

FPGA Design Engineer (10-12 yrs, Bengaluru)

Electronics & Semiconductor Engineer (4-15 yrs, Bengaluru)

PSP Firmware Engineer (5-9 yrs, Bengaluru)

ABL Firmware Engineer (5-9 yrs, Bengaluru)

WDD Engineer, Windows Device Driver (5-9 yrs, Bengaluru)

LDD Engineer, Linux Device Driver (6-10 yrs, Bengaluru)

HIL Test Automation (2-4 yrs, Pune)

Senior System Verification Engineer (9-12 yrs, Pune)

If you meet the requirements, DM me with your resume and a short summary of your experience, and I'll refer you.

In general, is it worth enrolling in an electrical engineering or chip design program? I would be grateful to hear about VUT from current students or graduates

Hey everyone,

I'm an ECE undergrad working on my first 5-transistor OTA in LTspice (using a TSMC 180nm process), and I've hit a wall with my AC analysis.

Getting the DC biasing right was a journey. I quickly learned that square-law hand calcs don't really survive contact with actual BSIM models! After some tuning, my DC operating point is finally solid: my tail current is sitting at ~19.6µA, it splits nicely to ~9.8µA per branch, and all transistors are well into saturation.

The problem is my AC sweep (1 Hz to 100 MHz). It is completely flat at around 36 dB.

I’m trying to find the unity-gain frequency (UGF) using a standard 1pF load capacitor at the output, but the plot just refuses to roll off. The capacitance acts like it is completely negligible. Through pure trial and error, I found that the gain only drops down to cross 0 dB if I slap a ridiculously massive 791.25 µF capacitor on the output. Obviously, that ruins the actual circuit characteristics.

Things I've already tried:

• Set up a true differential AC input (AC 0.5 phase 0 on one side, AC 0.5 phase 180 on the other).
• Plotted the differential gain explicitly instead of just testing V(out).

Even with all that, the 1pF response is still just a flat horizontal line at 36 dB all the way to 100 MHz.

Has anyone run into this? Is LTspice somehow ignoring my 1pF cap, or is there a known quirk with how the output pole behaves in these TSMC 180nm models under normal pF loads?

Hi everyone, I’m looking for advice on what to include in my resume in hopes of securing an analog layout internship for next summer.

I’m currently an undergraduate with some physical design projects (Innovus, Genus) and was able to obtain an analog-adjacent internship this summer using both schematic and layout editors in Virtuoso.

I really enjoy how there’s a bit of an “art” to the layout process that allows for some self expression. It was also fun fixing DRC/LVS errors from a puzzle perspective.

I’ve been applying early to recent internship postings in this field (Marvell, Qorvo, Skyworks) but I’ve yet to hear back, possibly due to a preference for graduate students. I plan on making more layout projects with Virtuoso, any other advice helps.

Can someone who interviewed or got selected for this role or a dv role at etched please give me a basic rundown of the rounds and process they have. Was the interview in person? What do they ask in screening round and what topics are covered in the interview rounds? Any tips and feedback is greatly appreciated.

Hi everyone. I am not that good in writing English so the text below is generate by AI, but the questions and context are mine.

The situation is that I’ve just started working on a personal project from scratch after finishing Razavi’s Design of CMOS. However, I’ve realized that there is a huge gap between theory and practice.

I’m currently designing a two-stage op-amp with five OTA transistors. When I watch YouTube videos, I often see people clearly define their specifications from the very beginning, such as gain, GBW, CMRR, slew rate, etc. What I don’t understand is how they are able to determine these specifications so precisely in the first place. More importantly, somehow, they manage to meet all of these specifications, at least to some extent.

As a beginner, I thought I would try limiting the number of specifications I work with, so I decided to focus on gain, power consumption, supply voltage, output swing, and phase margin.

However, this seems to make the problem even harder. For example, GBW and slew rate provide relationships between different parameters, such as gm and Cc, or I_ss and Cc . With the specifications I’ve chosen, though, I’m still struggling to figure out how to select appropriate design parameters and establish meaningful relationships between them.
Another issue is that I’m not sure what the right approach to the design process should be.
For example, suppose I start with the gain requirement. If I want a gain of at least 60 dB, then theoretically, the product of the gains of the two stages (A1 and A2 ) must be at least 1000. My initial guess would be to allocate a gain of 50 to the first stage and 20 to the second stage.

Then, for example, I could express the second-stage gain as gm_p * (ro_p // ro_n)

The problem is that, in nanometer-scale CMOS design, gm and ro can vary significantly and behave quite poorly as functions of square-law and other related parameters (at least with the pdk I am having). This makes it really difficult for me to determine the appropriate values and figure out how to proceed with the design.

So, I’d like to ask the community two questions:
How do you choose specifications that are interconnected? In my case, if I deliberately limit the number of specifications, is there a way to determine suitable design parameters and establish relationships between them?

What is your general approach to calculating and designing a circuit? In particular, how do you approach hand calculations when working with nanometer-scale devices, where the models seem to become noticeably less accurate and the device characteristics are much less ideal?

I’d really appreciate any advice or insights from people with more experience in analog IC design!

Edit: Sorry for the missing parameters in the text. I have updated.

Hello. As the title says, I am designing a capless LDO and using class AB error amplifier + PMOS gate drive buffer. I have massive PM of like 160 degrees and my VOUT is oscillating around the desired value.
How can I optimize this design to have a good stability and transient response? Any resources will be helpful also.

Hi, I’m an MS(Research) student in the mixed-signal domain, currently on a long leave from clg.

Before my masters, I worked for around a year as a Verif Engineer, mainly building block-level IP testbenches using Python/cocotb.

Since Sept, I’ve started building an 8-bit processor from scratch (not RISC-V) with a custom ISA. I’m also trying to strengthen my verification skills by working on bus protocol verification, moving from cocotb towards pyUVM.

On the analog side, I’ve been watching lectures from different channels and curated a roadmap covering topics from analog circuits to analog IC design. I’m also solving problems from books/workbooks wherever I can find them, but I haven’t done any hands-on circuit design or SPICE simulations yet.

Digital seems interesting to me, but I’m not sure whether I’m leaning towards it simply because I have more experience with it and haven’t explored practical analog design yet.

Given my situation, does it make sense to continue in mixed-signal and explore analog design properly before deciding, or should I focus more on digital design?

Also, how would you suggest getting started with hands-on analog design?

Hii All, Is anyone here working or have worked on Polar modulated Power Amplifiers? I would like to get some guidance for my masters thesis. Thank you

Hi, I was wondering if my resume would be good for any roles in ASIC/DV/RTL/CompArch. I've been applying but haven't been able to get any interviews yet and I wanted to see if I could any suggestions on what to change or add. Only have experience with embedded software since it's the only offer I got, however have been trying to target getting into chip design industry. Also would want to know what projects could help me standout for AI Hardware roles.

In the JS standards, you have certain precharge voltages assigned to certain current waveforms (ie, for HBM for a 2kV cap precharge, you need a current waveform that achieves a peak current of ~1.4 A) In these standards, if you don't achieve this, they say to clean the tester, or change the precharge voltage until you do achieve the right current waveform. My question: If I am to simulate an HBM/CDM event in cadence, is it sufficient to use a current source referenced to a PWL file of a passing current waveform as the stimulus to my port? Why or why not?

Hi everyone, I’m a thesis-based ECE master’s student at UVic in BC, Canada looking for semiconductor co-ops in RTL design, DV, validation, CAD methodology and emulation.

I’ve applied to 50+ semiconductor-related positions so far, and I’ve received a few interviews, all from Microchip and Solidigm in BC, but none from Ontario companies, where I’ve seen more relevant postings.

I’m an international student and willing to relocate. I have physical implementation training and FPGA/Verilog/SystemVerilog projects. My master’s research is in machine learning, so it isn’t directly related to RTL/DV.

For people familiar with Canadian hiring:

• Do Ontario teams mainly recruit through particular universities/co-op programs, or regularly consider students from BC?
• Could being a master’s student with an unrelated thesis affect shortlisting? What would help demonstrate my fit?
• What helped you get your first semiconductor co-op in Canada?

I'm just trying to understand the pattern and improve my approach. Any insights would be appreciated!

Hi all,

I have an interview at Marvell for a silicon engineering internship role. The job description seems like its mostly rtl design and verification.

Anyone know what the interview questions might look like? Thanks

I have lowkey been spiraling the past few days about AI not necessarily taking my job, but making it so utterly boring I would want to quit. I am about to finish my masters and start at a large tech company, but with the way that AI has been progressing especially in RTL and digital design I just don't see a world where I can out compete it. Every project I've been given in grad courses or internships can so much more easily be done by AI than me. At the large tech companies now, managers don't even care if you understand things they just want things to be shipped out as quickly as possible. Those of you that are both new and experienced in your careers what are your outlooks? There is so much unknown as far as future career in digital design goes that I am unsure if I should just end up changing professions. I used to love engineering and fell in love with computer architecture, but now it just seems like AI can do it all way better than I can and it takes the fun out of engineering.

Hello,

I recently got a technical round email for the front end sta role in apple hardware team….I have attached the preferred qualifications screenshot

Has anyone been interviewed for this role…please share your experience what questions i can expect and stuff…. I’m a physical design intern so I dont know what to study or expect for this role i just have a brief overview

Any advice from front end people helps…put in interview topics…youtube playlists…anything relevant that you have

FYI: I am a masters student graduating in December, My interview is next week. Currently interning for a pd sta intern role.

Just finished my final round for an Apple hardware internship, and a couple days later my recruiter asked for my transcript, summer availability, and any competing offers or deadlines. Is this a good sign or just standard procedure? Anyone had something similar happen, and did you end up getting an offer?

Has anyone taped out a chip in IHP or tiny tape out to help boost their resume for a job swap? Let’s say jumping from low speed analog to RF? Or digital to analog etc.

Trying to think like an RTL designer.

I am running into situations in my learning journey where I challenge myself to consider new requirement or edge case which then challenge my original implementation.

In resolving such things, do I prioritize finding minimal changes to preserve my existing RTL, or be willing to restructure the design entirely, even if it means rewriting significant portions? Also doing this for interview prep. What is preferred?

How do experienced RTL/ASIC engineers decide when to patch versus redesign?

(Yes I know, in the real world AI can do it for me in 37 ms).

Guys i basically landed an on campus interview for the said role in NVIDIA. Since the OA only had maths, I was able to get shortlisted for interviews pretty easily. The thing is I have actually transitioned to software development and AI research entirely. Like I do quite a bit of competitive programming and I have published a paper related to computer vision with more coming on the way. Given all this I don't even remember how even tmux's work....it's not completely unfamiliar but I don't remember much cuz I did this course like 5-6 semesters ago.

Now I can't study for this since I also have another interview parallel to this for a computer science related role in a lesser company (Mathworks) but well i don't mind getting hired for any of those. Any tips on how to keep the interviewer on maths, puzzles and programming side?