Can someone who interviewed or got selected for this role or a dv role at etched please give me a basic rundown of the rounds and process they have. Was the interview in person? What do they ask in screening round and what topics are covered in the interview rounds? Any tips and feedback is greatly appreciated.

In general, is it worth enrolling in an electrical engineering or chip design program? I would be grateful to hear about VUT from current students or graduates

Hi everyone,
I’ve completed all 4 interview rounds for a Google India Verification Engineer role, with positive feedback. HR then asked for some additional information, and it’s been around a week.

HR now says “the team is reviewing my feedback and will make a final decision regarding my level and next steps. They also clarified that the decision depends solely on my candidacy, not other candidates.”

Has anyone experienced this? What does this stage mean, and how long did it take to get the final decision?

Hello,

I was recently in an interview wherein I was asked simple questions about poles and zeros in a single transistor circuit, and bode plots and two stage op amp design. I know these topics, but as soon as a new question comes up, I mess it up. Where can I get practice questions to help me prepare better ? I have solved Razavi’s exercises, but I can’t apply myself on the interview. Are there any other helpful materials?Any suggestions are welcome.

Thanks !

Italy was one of the first countries to implement the new EU directive that makes companies having to reveal a salary range for the positions they post.

I am baffled by how low these companies put their wages.

Less than 5 YoE? Expect a salary in the 30k to 39k range. Want 50k or more? Only with 7+ years.

And this is not for small villages in the middle of nowhere, it is in cities like Milan where the cost of living is crazy expensive. Moreover, if the company has offices in multiple locations they don't adjust their compensation to reflect the cost of living differences. It is a fucking joke, it is like they are lowballing as much as they can to see who accepts it.

I have been trying to change jobs but honestly feel more and more discouraged to apply to Italy, and it also makes me angry how people can accept such low conditions. Please remember that by accepting such a low wage you are not doing a favour to anyone but these greedy companies. It worsens the market for everyone.

Hey everyone, I’m more of an FPGA guy than an ASIC guy.

We’re building openTPU, an open-source AI accelerator with the whole stack in one repo: architecture, RTL, ISA, simulator, compiler, and host tools. It already runs some pretty respectable models like Qwen3.5 on a Kintex-7 PCIe card.

With help from the community, we’ve now routed our first design using Nangate45. I’d love to get some ASIC eyes on it, especially on the floorplan, timing constraints, and anything we might be overlooking as we move from FPGA to ASIC.

Feedback, contributions, and a good technical roast are all welcome. If you love this stuff, come have fun with us.

https://github.com/FeSens/openTPU

Not sure if this belongs here as I posted on r/ece

Hey everyone! So I am planning on heading into my Accelerated Bachelors Master program. I won't start until Fall 2027 and I've been told it would reduce my time significantly at my university even if I pursue a PhD. So what I want to do is design the hardware what I am looking into and actually am good at is Digital Circuit design in VLSI, ASIC/FPGA, CMOS, and possibly Computer Arch if I can fit it in, I highly doubt I can. Point is I am already an undergrad researcher and in a fellowship. I am actually not doing research in my field but it is consider a material that translate to EE. I do not want to go into my masters and take classes that I may dislike. So far I like what I am learning but I want to make sure this is where I want to be.

What is the day to day life like?

Will I have time for my family and friends? How about hobbies?

How will I know if this is for me without getting exposure or do I actually need exposure?

I do not want to regret my decision. How did you know this was the right career path for you?

If given the stipend to continue research and pursue a masters or PhD which should I aim for?

Are there any project I can do currently?

Lastly, of course how is the salary in today's economy and is employability high for this type of work?

Hey everyone,

I'm an ECE undergrad working on my first 5-transistor OTA in LTspice (using a TSMC 180nm process), and I've hit a wall with my AC analysis.

Getting the DC biasing right was a journey. I quickly learned that square-law hand calcs don't really survive contact with actual BSIM models! After some tuning, my DC operating point is finally solid: my tail current is sitting at ~19.6µA, it splits nicely to ~9.8µA per branch, and all transistors are well into saturation.

The problem is my AC sweep (1 Hz to 100 MHz). It is completely flat at around 36 dB.

I’m trying to find the unity-gain frequency (UGF) using a standard 1pF load capacitor at the output, but the plot just refuses to roll off. The capacitance acts like it is completely negligible. Through pure trial and error, I found that the gain only drops down to cross 0 dB if I slap a ridiculously massive 791.25 µF capacitor on the output. Obviously, that ruins the actual circuit characteristics.

Things I've already tried:

• Set up a true differential AC input (AC 0.5 phase 0 on one side, AC 0.5 phase 180 on the other).
• Plotted the differential gain explicitly instead of just testing V(out).

Even with all that, the 1pF response is still just a flat horizontal line at 36 dB all the way to 100 MHz.

Has anyone run into this? Is LTspice somehow ignoring my 1pF cap, or is there a known quirk with how the output pole behaves in these TSMC 180nm models under normal pF loads?