LTspice AC analysis flatlining at 36dB with a 1pF load (TSMC 180nm 5-T OTA). What am I missing?

[u/OutrageousSpecialOne]

Hey everyone,

I'm an ECE undergrad working on my first 5-transistor OTA in LTspice (using a TSMC 180nm process), and I've hit a wall with my AC analysis.

Getting the DC biasing right was a journey. I quickly learned that square-law hand calcs don't really survive contact with actual BSIM models! After some tuning, my DC operating point is finally solid: my tail current is sitting at ~19.6µA, it splits nicely to ~9.8µA per branch, and all transistors are well into saturation.

The problem is my AC sweep (1 Hz to 100 MHz). It is completely flat at around 36 dB.

I’m trying to find the unity-gain frequency (UGF) using a standard 1pF load capacitor at the output, but the plot just refuses to roll off. The capacitance acts like it is completely negligible. Through pure trial and error, I found that the gain only drops down to cross 0 dB if I slap a ridiculously massive 791.25 µF capacitor on the output. Obviously, that ruins the actual circuit characteristics.

Things I've already tried:

• Set up a true differential AC input (AC 0.5 phase 0 on one side, AC 0.5 phase 180 on the other).
• Plotted the differential gain explicitly instead of just testing V(out).

Even with all that, the 1pF response is still just a flat horizontal line at 36 dB all the way to 100 MHz.

Has anyone run into this? Is LTspice somehow ignoring my 1pF cap, or is there a known quirk with how the output pole behaves in these TSMC 180nm models under normal pF loads?

[u/flextendo]

Thats not how you check the open loop gain. Bring it into unity gain feedback and break your feedback loop using a very large L in series between your output and inverted input and a large C to ground (inverted input to gnd). Tiny systematic offsets will push your design into saturation at the output.

This makes sure your DC operating point is stable, while creating an „open“ condition for AC.

[u/positivefb]

I quickly learned that square-law hand calcs don't really survive contact with actual BSIM models!

They're not exact but at 180nm they're close than you're making them out to be, you're just doing it incorrectly. You should never be finely tweaking numbers to get an exact voltage like this, it would be so impractical to get 0.56V anywhere on-chip, and even if you did the transistors vary enough that 0.56V would work for only a few out of a thousand chips. Dwell on that for a few moments.

Biasing: this is not how you bias your tail current. Dont apply a voltage source, apply a current source to a diode-connected transistor and tie their gates together to form a current mirror.

Open loop gain: you can't properly characterize an op-amp's open loop gain by literally having it in open loop like this. Connect the output back to the input using a voltage source that has DC=0, and AC=1, remove the AC statement from the other voltage source. See here for example.

Closed loop gain: set that voltage source's AC to 0 as well, and set V3's AC back to 1.