hey there

I'm very new to RF and I'm planing to simulate a hairpin BPF [freq = 1420MHz, BW = 10%, teflon substrate with a relative permittivity of 2.94]

It's intended to be used to filter out unwanted frequencies, before the signal gets processed in a SDR V3

I'm currently trying to simulate the coupling coefficient of two hairpins in HFSS.

I've made the ground plane roughly as big as my pcb will be, wich is 130x120mm. [I'm planning on making an 8way wilkinson combiner to connect 8 different yagi antennas, then the signal will pass trough the BPF, then a LNA and then finally into the sdr v3]

As I cannot make the feeding line to long, and therefore I have problems placing the input/output ports at the outher edge of the "pcb", I've just placed lumped ports "in the middle" of the pcb.

Is my setup somewhat okay?

I think something is VERY wrong but i just cannot figure out what to do

I thought I'd get results like this:

But my simulation looks like this [with a spacing s between the two hairpins = 0.09mm]

I've also added Z(2, 1) and Z(1, 1) traces, I don't know how but maybe that'll help

My plan would be to graph the coupling coefficient for different distances s, and then built my BPF according to these results.

Can someone see my mistake and please give me some advice?

thanks

Has anyone found deliveries of R&S test gear has become awfully long, like it’s normally 14 weeks or so, and one day before it should arrive, stretched out another 8 weeks? This is not a small power supply, but VSG’s, a VNA, MXO4 scope etc. I know they have Dram in them, but seriously….

Hello!

I am currently working on a project where we use 250 watt RF input power.
I'm looking to design a PCB-based Marchand balun, the design uses coupled transmission lines on two dielectric layers with a common ground plane.
Would this be possible without burning the PCB, what should i look for when simulating (for the 250Watt part)?
I am using Rogers4350B and frequency are 1.4-1.7GHz

BR Me

Hii All, Is anyone here working or have worked on Polar modulated Power Amplifiers? I would like to get some guidance for my masters thesis. Thank you

Follow-up to my previous post on updates to the Tiny RF Simulator Project.

Since then there have been 27 releases, v0.20.1 through v0.28.2. Full notes are in the CHANGELOG and on the releases page.

Receiver and analyzer

• Receiver Requirements panel: set a frequency band, an acceptable gain range, and a maximum noise figure. Each sweep gets pass, fail, or incomplete per metric and overall. Limits save with the project.
• Output-power and two-tone IIP3 requirements, with configurable tone spacing and input-level sweeps.
• Network Analyzer and receiver requirements now measure paths through a 1:2 switch feeding parallel branches that rejoin at a 2:1 switch. Combiner paths still report no data.
• The PFB inspector reports integrated channel noise and effective noise bandwidth. Its hover SNR uses channel noise, not the analyzer's RBW.
• Spectrum analyzer RBW and VBW now go from 1 kHz to 100 MHz. Network Analyzer gain and noise-figure plots autoscale.

New parts and instruments

• SPDT RF switches, 1:2 and 2:1, with insertion loss and isolation settings. The unselected path leaks in at the isolation floor.
• Power Meter: total power in dBm from any signal-node output, whether tone-only, noise-only, or combined.
• PFB filter calculator: synthesizes a Kaiser prototype, reports achieved metrics against the rejection target, and applies the design to a PFB channelizer.
• Hovering a node shows the strongest-tone SNR at its first output.

Test flows

• A GUI-free test-flow runner. A JSON file sweeps component parameters and records measurements, and results export as JSON.
• The Test Flow panel (View > Test Flow) runs those files against the live circuit.
• The panel can now write flows: pick a component and parameter, add conditions and measurements, save, and reload.
• Results report the value a component actually applied after normalization. A requested ADC decimation of 3, for example, reports 2.

Agent interface (MCP)

• An MCP client such as Claude Code can read and edit the circuit in an open simulator window. Enable Agent Server under View > Agent. The rf-sim-mcp bridge ships in the release archives.
• Agents can read the circuit, run port measurements, network-analyzer sweeps, receiver measurements, and test flows. Each call can apply up to 64 edits with checkpoints. Reverting a checkpoint needs confirmation.
• Agents cannot open, save, or name files (yet)

Editing and projects

• Swap a placed library part in place. The new part keeps the old part's id, position, links, and probes. A swap is refused, with the reason shown, if the new part lacks a port that is wired, probed, or used by an instrument.
• The editor rejects a second link into a single-source input and any link that would create a cycle.
• Out-of-range values stay as loaded and are flagged in amber. Previously the limit replaced them on the next edit.
• The header shows the project's Git commit and counts of staged, unstaged, untracked, and conflicted files.
• Hover tooltips list the interaction hints: Ctrl+click probes, Shift+click removes a probe, right-click opens the menu.
• User manual, part 1 of 3 (install and a guided tutorial), is in the repo under manual/pages/.

Fixes that change results

• Ideal-mode amplifier H2/H3 distortion was inflated by 2G/3G dB because gain was applied as a power ratio. It now matches the S-parameter branch.
• Ideal low-pass, high-pass, band-pass, and band-stop filters compare each bin's magnitude, so complex-baseband (ADC) spectra filter symmetrically. A negative-frequency blocker is now rejected by a low-pass filter.
• Equalizers and mixers handle negative (complex-baseband) frequencies correctly.
• Combiner added noise is clamped at zero. A negative term had been reported as InvalidNoise.
• Projects saved before the sparam_filepath rename now load their S-parameter files instead of falling back to the manual model.

Behavior changes

• Project-local extensions need one Trust click before they run. A project extension that reuses a built-in or global ID is reported as Shadowed and does not run.
• Ideal filter library definitions must set their cutoffs. Low-pass and high-pass need fc_low_Hz. Band-pass and band-stop need fc_low_Hz and fc_high_Hz. Definitions without them are refused instead of using the 100 and 200 MHz defaults.

What should the next update(s) cover?

For the past few months, in our free time, a colleague and I have been building a tool for hardware designers. It’s called ACE, and before moving forward, we’d like to see if it actually makes sense.

The idea stems from a personal frustration. If you ask ChatGPT for the noise figure of an amplifier, it responds with absolute confidence. But it’s not actually reading the datasheet: it just hallucinates the most likely number based on its training data. As a result, you get a value measured at a different frequency, or from a similar model, or a "typical" value presented as guaranteed—and nobody tells you where it came from. It also does math "by eye": one mistake in an RF chain calculation, and the whole result is wrong, written with the exact same confidence as a correct one. You only notice it when the board arrives.

ACE, on the other hand, answers strictly based on datasheets. Every value displays the exact page and measurement conditions right next to it, so you can double-check it in ten seconds. The code handles the calculations using transparent formulas, not the AI model. If a data point isn't there, it tells you instead of making it up.

Right now, it's a prototype: it includes about 1,500 datasheets, mostly RF, and some features shown in the video are still in the early stages.

To the hardware designers out there: would you use this? And what would it take for you to truly trust the numbers? We are especially looking for critical feedback.

Guys so I'm building a rectangular microstrip antenna in HFSS for mmwave applications. Resonance at around 28 GHz. I am getting vswr<2 bandwidth of around 1.5GHz. How can i improve this. It's just a simple inset fed microstrip line. Please give me some resources or tips to learn on increasing impedance bandwidth

Title: Question about Amphenol connector HFSS model - How to handle the extra solder block?

Hi everyone,

I'm currently working with an HFSS simulation model for an Amphenol connector. I noticed there is an extra piece of geometry right at the feed location.

I reached out to the vendor, and they explained that this extra block represents the solder.

My question is: how do you all usually handle the height difference / Z-axis gap issue caused by this extra solder block when integrating this file into your own simulations? Do you modify the connector model, or do you adjust your PCB stackup/layout to accommodate it?

I've attached a picture for better context. Any advice or experience with this would be greatly appreciated. Thanks!

Hello, I would like to know if I can use FR4 for my RF power amplifier operating at a narrowband frequency of 805 MHz. I initially designed the amplifier using RO4350B, but few US manufacturers supply that substrate, and it is more expensive, even though it is the material used by the vendor of my BLP981 transistor. I know FR4 should work well at that operating frequency, but given that I am generating 100 W, I think that could pose a problem. Could I use FR4?

Hey everyone! I’ve been working on Fairbeam, a free and open-source app for designing and simulating antennas, and thought some of you might enjoy trying it.

It brings 3D modeling, meshing, simulation, and plots into one workspace, using openEMS, CSXCAD, and three.js. You can draw a model visually or use Python, then inspect S-parameters and radiation patterns.

It’s available for macOS and Windows, with experimental Linux support. Optional GPU acceleration uses CUDA on NVIDIA GPUs and Metal on Apple silicon.

It’s still early, so I’d love to hear what feels useful, what’s confusing, and what breaks. The code is GPL-3.0-or-later. Feel free to dig in, change things, or contribute an example!

Website: https://fairbeam.org

Code: https://github.com/ismailakdag/fairbeam

As with any simulation tool, please check the results against a reference you trust.

Okay this is a bit open-ended so it might be hard to answer but here goes. With current technology, is it feasible to pack about ~200 diodes (well, junctions) into a ~30mm linear strip*? These junctions would be operating at very low current but around 100V, at say ~5 MHz. No this isn't for energy harvesting!

(*okay lets compromise and call it a square - how much area would I need to stuff 200 diode junctions into?)

Hi all,

For the past while I've been building a Windows tool for first-pass antenna design, and I'd really appreciate feedback from people who do this professionally (or as serious hobbyists).

**The idea:** you enter the frequency and the constraints you already know (substrate, board size, trace width), and it gives you tuned dimensions plus the full picture – S11, Zin, Smith chart, 3D pattern, gain and efficiency – and fabrication files.

**What's under the hood**

- **Wire antennas** (dipole, monopole, folded dipole, loop, Yagi, biquad, helix, ILA, IFA): thin-wire method of moments, checked against NEC-2. Finite ground planes are modelled as a wire grid.

- **Microstrip patch** (probe / inset / edge + λ/4 feed): calibrated cavity/TL model for the dimensions, plus an optional full-wave check on the real, finite board (so you get back radiation and FR4 loss).

- **Printed IFA / meandered IFA:** a built-in FDTD solver (Yee, graded mesh, Mur ABC, NF2FF) tunes arm length and feed spacing. Several simulations run in parallel.

- **Arrays:** element pattern × array factor with uniform / binomial / Chebyshev / Taylor tapers and steering (no mutual coupling – see limitations).

- **Exports:** Gerber + drill, DXF, NEC-2, an openEMS script (so you can check it independently), Touchstone, PDF report.

**Example – 2.45 GHz printed IFA on 40 × 50 mm FR4 (1.6 mm):**

S11 = −32.9 dB at 2.45 GHz, −10 dB bandwidth 203 MHz, 2.26 dBi gain, ~90 % radiation efficiency. 7 FDTD runs, under a minute on a 2-core machine.

**Validation against openEMS (same structures):**

| Case | This tool | openEMS |

|---|---|---|

| Printed IFA, best-match frequency | 2.4405 GHz | 2.4408 GHz |

| FR4 patch, resonance | 2.393–2.401 GHz | 2.402 GHz |

| Patch on 150 mm board, directivity | 6.86 dBi | 6.96 dBi |

**Limitations (being upfront):**

- PEC metals (no copper loss); dielectric loss is included for patch/PCB.

- No enclosures, nearby components, cables or hand effects – you still need to measure and trim.

- Arrays use pattern multiplication, so no mutual coupling or active impedance yet.

- Windows only for now.

**What I'd love feedback on:**

1. Does this match how you actually do a first-pass design, or would you still go straight to HFSS/CST/openEMS?

2. Which antenna types or features are missing for your work (chip-antenna keep-out, coplanar feeds, mutual coupling in arrays, …)?

3. Anything in the results that looks off to you?

It's a paid tool, but there's a free trial that shows the full performance of every design (exact dimensions and exports are in the full version). Link in the comments if anyone wants to try it – happy to give free licenses to a few people who are willing to give detailed feedback.

Thanks!

Hi!

I'd like to know if anybody around here has found or made any schematics for a simple biased HF mixer using discrete components or has any NE612 biased equivalents. I'd like to use one for a homebrew HF DC receiver. I will miss the NE612...

A Rohde & Schwarz CMW500 recently arrived at our warehouse.

Took a few photos during the initial power-on check. It's interesting to see how many of these wireless communication testers are still circulating in the used equipment market.

Anyone here still using the CMW500 for wireless testing?

In this episode Shahriar investigates a faulty Agilent E8257D analog signal generator. These high-performance synthesizers are in wide use & high demand. The instrument fails self test procedure. The error code "704 Filter Test" generally points to the Frac-N module which also houses the modulus divider circuits. This portion is responsible for generating frequencies below 3.2GHz and uses an integer divider, filter bank and variable gain amplifiers.

Using a 12GHz active probe, the signal path (pun intended) is verified step by step from the input to the suspect sub-system all the way to the output of the Frac-N board. The fault is ultimately traces to a custom MMIC module with an Agilent GaAs FET amplifier circuit. A new replacement IC is sourced from eBay which clears the fault. The phase noise performance of the unit is also verified at 2GHz using an Agilent E5052B signal source analyzer.

Lastly, the faulty MMIC module is de-capped and the die is analyzed under a high power microscope with various imaging techniques.

I have two projects derailed now due to parts shortages. GaN/GaAs MMIC are the real problem, but clock drivers, certain FET, diodes, and even 1-10 uF MLCC. I think it’s actually worse than COVID now as that seemed to be limited to MLCC and microcontrollers.

Any one else having issues? I’m about ready to just throw in the towel and retire.