r/FPGA • u/Same-Classroom-4751 • 20h ago

First day using vivado

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23 Upvotes

89% Upvoted

9 comments sorted by

15

u/Bulky_Caramel_2234 18h ago

welcome to the kilowarning generator machine

3

u/mother_a_god 16h ago

Many of rhe warnings are useful i find. 

3

u/frankieinaprius 8h ago

The problem is all the useful warnings are buried amongst the non useful warnings.

2

u/mother_a_god 3h ago

You can suppress any warning you dont find useful using a tcl command in your project. Just give it a list of IDs 

My take - you're better looking at it than looking for it. 

4

u/Bulky_Caramel_2234 14h ago

Only critical warnings deserve attention

1

u/AlbbO_The_Great 4h ago

Warning, task executed successfully

3

u/Ateef_31 20h ago

Ur verilog code should be in design not in simulation while creating a file select create a design source, and to create the test bench select the create simulation source.

1

u/jonasarrow 19h ago

It is a design file, but as there is no tb defined (which also does not include the buff.v) Vivado automatically selects that as the top file for simulation and synthesis.

OP, you are good so far. Add a second source (the testbench), and select simulation only as the type. There you can define stimuli, add your buff as a component to drive your buff.v . If you do not need simulation, you can directly go to synthesis and implementation (see the entries on the left or start it in the "design run" tab on the bottom with a right click).

1

u/jacklsw 2h ago

overwhelming.