r/FPGA • u/SupermarketFit2158 • 22h ago

Advice / Help Alternatives to uart or pre processing on a pc for my project

I made a working correlator receiver in VHDL for my basys3 that can read from a raw IQ .bin file captured by an RTL-SDR and decode and display airplane positions and information. I want to make it work in real time and not just simulations but im having trouble figuring out how i can get the RTL-SDR stream to the basys3 without doing all of the signal detection on a pc first.

From what i understand the basys3 uart maxes out at 1 Mbps but adsb raw IQ sampling needs at least 32 Mbps. This is my second project on the basys3 and i dont have any other hardware but im open to any (cheap) suggestions that make this as little pc dependent as possible.

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u/tux2603 Xilinx User 20h ago

If you want to be ambitious, you could implement enough of the USB stack to plug the rtl sdr directly into the basys3. That'll be hard though. Another option would be to find/build an sdr that can be plugged directly into your FPGA's gpio pins

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u/SupermarketFit2158 19h ago

Its just a side project to learn more about vhdl and fpgas so im not limited on time or anything, definitely going to look into the usb thing that sounds awesome

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u/heeler-side-eye 18h ago

If you’re trying to transfer data in “real time” between a PC and the FPGA the one of the usual ways to do that is a PCIe link, from there you can use something like XDMA to bridge PCIe to AXI/AXIS. If you had DDR, I’d say load IQ into that using a DMA. Obviously that’s not going to work on this board.

Basys 3 looks pretty limited on high speed IO. It does have a USB port on it but that appears to be limited to HID input (appears to have a PIC24 managing that for ease of use getting USB HID up for students). Not sure what kind of peripherals you can get for the PMODs but I know digilent offers a bunch. Maybe if they have a 100Mb Ethernet PMOD you could find a way to utilize that + some IP? Probably has enough bandwidth for this case.

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u/InterWiser 8h ago

Since your correlator already works with recorded IQ samples, I'd keep that part unchanged and solve the transport problem separately.

At 2 MSPS with 8-bit I and 8-bit Q, you're moving 32 Mbit/s before any framing overhead. So UART isn't a realistic option for continuous raw IQ streaming.

One approach worth looking into is an FT2232H-based USB FIFO interface. The PC would still receive samples from the RTL-SDR, but it would only forward the raw IQ bytes to the FIFO bridge. All the actual ADS-B detection and decoding would happen in your FPGA.

You'd need to check the FIFO mode supported by the specific FTDI board, available FPGA pins, voltage compatibility, and sustained throughput. Add a FIFO in the FPGA so your processing logic doesn't depend directly on the incoming transfer timing.

I wouldn't start by implementing a USB host stack on the Basys 3. That's a much bigger project than the ADS-B receiver itself.

If your eventual goal is to remove the PC completely, you'll probably want an SDR front end with an interface the FPGA can receive directly, or a different FPGA board with suitable high-speed connectivity.

For now, I'd get the live IQ stream into the FPGA first and verify it against your existing recorded-data testbench.