r/FPGA • u/Acceptable_Trade_966 • 1d ago

News SILICON — An open-source digital circuit simulator built with C++ and Qt.

Hi!

I'm the developer of SILICON, a free and open-source digital circuit simulator written in C++ using Qt6.

It's going to become my Bachelor Thesis (I'm studying Computer Engineering @ Genoa Italy) and we are exeperimenting with It in the digital design course at my university (UniGe).

SILICON aims to provide a modern environment for designing and simulating digital circuits, primarily for educational purposes (like LogiSim), while gradually incorporating more advanced EDA capabilities.

Some of its current features include:

• Graphical circuit editor with logic gates, arithmetic components, flip-flops, registers, ROMs, and more.

• Event-driven digital simulation with multi-bit buses and four-state logic.

• Live waveform visualization and input waveform editing with FST firstclass support.

• Verilog import/export through Yosys integration.

• Automatic circuit placement.

• Reusable subcircuits and multi-document projects.

• Integrated code and binary editors, along with experimental ISA tooling.

• WASM web build

I'd especially appreciate feedback about the user interface, simulation behavior, missing features, and any bugs you encounter.

If you want to contribute as a dev send me a DM. I especially need help with MacOS support and Windows packaging.

23 Upvotes

75% Upvoted

29 comments sorted by

26

u/Enlightenment777 1d ago edited 1d ago

1) Another generic named tool that will be impossible to find.

Have you ever consider how hard "Silicon" will be to find via Google search?

2) Your webpage needs far more complex visual examples than 2 gates.

0

u/Acceptable_Trade_966 1d ago
  1. I actually know but the Logic subsystrm will be called SILICON LogiFlow once there will be the necessity. (For now Just search SILICON Logic simulator). It's kind of a tradition of my university to have common used names (the predecessor was called DEEDS).
  2. The website will be updated with the first stable release, the first beta was released on Friday. I have in Plan a full docs section with tutorials / complete lessons

9

u/Enlightenment777 1d ago edited 1d ago

I'm aware of DEEDS, and you should include something about it when you promote this new software, otherwise people may suspect your software might be another AI-developed crapware, since there has been a mountain of it being pushed out during the middle of this year.

https://www.digitalelectronicsdeeds.com/index.html

1

u/Acceptable_Trade_966 1d ago

Well the AI usage policy in the GitHub repo speaks for itself ;)

4

u/sylogizmo 1d ago

I think you vastly overestimate how eagerly people read policies, licences or codes of conduct. ;)

1

u/minecon1776 13h ago

Just call it logiflow now then. This will make current information googlable in the future

2

u/UnhappyReputation513 1d ago

I'm interested in this. How would you say it's different than logisim?

2

u/Acceptable_Trade_966 1d ago

First class HDL / Yosys integration with circuit autoplacement, modern simulation engine with delayed components, convergence analysis, SCC decomposition for circuits with feedback, support for FSTs waveforms and raw binary files. It will be a sweet spot between Logisim and Vivado.

1

u/NaturalCommand3579 1d ago

WHY???

1

u/Acceptable_Trade_966 1d ago

Cause I wanted a native app, with Verilog first-class support (import/export) that could simulate delays for use in classroom

0

u/NaturalCommand3579 1d ago

Bro, no offense but don't waste your time building things like this; it's better to spend time designing some digital systems than replicating existing tools using AI, which adds literally no value. You are still using yosys, iverilog etc under the hood right. This is just a fancy GUI if I am not wrong. Just take it as an advice.

1

u/Acceptable_Trade_966 1d ago

No. I've written the simulation kernel from scratch. Yosys is only useful as Verilog Converter

1

u/Far_Outlandishness92 1d ago

Can it import verilog or from Logisim?

1

u/Acceptable_Trade_966 1d ago

It imports Verilog (using Yosys) and it converts it to a graphical circuit

1

u/Far_Outlandishness92 1d ago

I have a 70.000 line project across some hundred modules - would it be able to handle the hierarchy?

2

u/Acceptable_Trade_966 1d ago

From a Verilog POV yes, the problem might be auto placing. EDIT: Also, not all cells are currently supported

2

u/Far_Outlandishness92 1d ago

I will have to try 😊

1

u/Acceptable_Trade_966 1d ago

Keep in mind it's still a beta. Let me know :)

1

u/Zarathustra_04 1d ago

Bookmarked

1

u/Beautiful_Stage5720 1d ago

This website SCREAMS ai generated

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u/Acceptable_Trade_966 1d ago

Yeah the website is just a beta, the real asset is the code

3

u/Beautiful_Stage5720 1d ago

Its a red flag. People are generally gonna suspect the entire project is just AI slop if you have an AI generated site. Most would rather see some god awful early 2000s style html than AI generated garbage.

2

u/Acceptable_Trade_966 1d ago

Not students trying to download a software tho. Could you help me with unsloppifying the frontend?

1

u/Beautiful_Stage5720 1d ago

"Built for hackers."

Is it? In what way?

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u/Acceptable_Trade_966 1d ago

It integrates with yosys and FST could generate Verilog from a graphical circuit and a graphical circuit from Verilog. It can read Yosys Json, so the code could run arbitrary synthesis passes

0

u/Beautiful_Stage5720 1d ago

What does that have to do with hacking

3

u/Acceptable_Trade_966 1d ago edited 1d ago

Hacking as in tinkering, as in being integrated in the open source ecosystem (read the jargon file as a reference)

  1. A person who enjoys exploring the details of programmable systems and how to stretch their capabilities, as opposed to most users, who prefer to learn only the minimum necessary.

  2. One who programs enthusiastically (even obsessively) or who enjoys programming rather than just theorizing about programming.