from analog circuits lab, since we're ahead of the lectures, I don't know how to do it, we're working on a basic NMOS differential amp

Here's the diagram:

and the circuit I made in the simulation:

I know that Gm is set as the derivative of I_out with respect to V_in.

In our case, we're checking the differential signal, which we set to be vdif, but we have no idea how to measure I_out, as the current in each branch should be equal, from what I understand.

We calculated the gain Av to be the derivative of (VOUT1-VOUT2) with respect to vdif, which gave us an inverted bell-like shape. We saw that in the book Av=-Gm*Rd, and saw that the graph of Gm looks exactly like minus the gain, so we know we're on the right track.

We need to show that the Av we calculated this way is equal to the product -Gm*Rd, so for that, we need to calculate Gm, which we don't know how to do.

Just to reiterate, it's the transconductance of the circuit as a whole we're looking for, not any particular transistor or branch.

The general procedure to find Gm in such circuits, if explained, could be a huge help for us.

Thanks in advance for any help.

I can't solve for the initial condition of V'c I have everything else with tis problem correct, however when i solve for this condition I get 8800 which is wrong. My current equation is Vc' + 5 Vc + 6 integral from 0 to t of il = 5Vs which gives my 8800. What am I doing wrong to solve for this initial condition?

Hello.

Is there any way or tips to systematically know which meshes must I perform mesh analysis to get the necessary equations?

Like in this example.

Thank you very much.

Hi, sorry if the wording in the title is wrong Im not studying EE in english. Basically the question of the assignment is what should RL be to maximize the power that is generated in it (or absorbed I guess, again Im sorry if the wording is wrong). I know that the power is maximized when the load resistance is equal to the source resistance.

So I short circuited the voltage sources and opened the current sources so the load is (R3+R2)*R4 / R3+R2+R4. Basically resistors 2 and 3 in series parralel to resistor 4. This is the right result according to the book as well but, and this is whats bothering me, I can't figure out why I cant do the opposite, why cant it be R4+R2 parallel to R3? The only thing that comes to mind is that maybe its because R4 is in the middle of the terminals of the load resistance so maybe it would affect that, but I have no idea and I feel like I just got lucky I went from the left to right , and on the exam I could just as likely do the opposite and get it wrong.

Thank you and I hope you understood what I meant!

Hello, I am not sure if this is the correct place to ask this question. I have been trying to make a current subtractor, I fixed the current mirrors fluctuating a lot by changing the dimensions and using cascode current mirrors. However, there is still a lot of interference between the 2 sets of current mirrors providing I1 and I2. could anyone help me out here?

I need the design of the BAS, maybe the as-built, with BOQ and the design estimation. I try looking online, but I cannot find BAS that is actually implemented.

 I am a complete beginner to FPGAs and just got a Digilent Nexys A7 (Artix-7) board. I'm coming from a MATLAB background and was hoping to use it for programming, but it looks like that's not really supported.

My goal is to get a grasp of how FPGAs work by implementing some core EEE projects, specifically focusing on PWM generation and extremely fast sampling for ADCs.

Since I have to use the Xilinx (AMD) tools, I'm a bit lost on what I actually need.

• What is the ideal software I should be using? I've seen "Vivado" mentioned. Is this the right free one for a beginner?
• Does this free version come with a good simulator included? That's a must-have for me to verify my designs.
• Will it fully support the Artix-7 chip on my board?

Any help pointing me in the right direction for the setup would be a huge help. Thanks!

I have a pretty wide width that I'm trying to use fingers for. I would also want to drain share. I have this stick diagram for a back to back inverter with no fingers down below and I would like this with 2 fingers

Topic: Undergraduate Electronics Engineering Digital Logic Design Sequential Circuits / Counter Design

Problem:

I’m trying to design a synchronous counter using T flip-flops for the sequence 2 → 4 → 2 → 1. The problem is that when I move from the state table to the K-map, one of the K-map cells needs to be 0 and 1 at the same time because the state “2” repeats in the sequence. I think this happens because “2” leads to two different next states (4 and 1), but I’m not sure how to fix it properly.

Givens/Unknowns/Find: Given: Sequence: 2 → 4 → 2 → 1

Unknown: Proper state encoding and logic equations that avoid K-map conflict

Find: How to handle the repeated “2” (state splitting or other method) so the counter cycles correctly using T flip-flops

Equations and Formulas: Standard T flip-flop excitation: Q(next) = T ⊕ Q

Used normal process: State diagram → Excitation table → State table → K-map simplification

What i have tried: 1.Drew the state diagram 2.Created the excitation and state tables 3.Used binary encoding for states 4.When simplifying K-maps(of T2 and T0 flip flop), conflict appeared because one cell needs both 0 and 1.

I suspect the fix is state splitting (like 2a and 2b) but I’m unsure how to encode or implement that with T flip-flops. Would appreciate an explanation or reference for how to design counters with repeated outputs or overlapping states.

Hey all, Im doing this problem using superposition, and im stuck on the 12A source. When I isolate for just the 12A source, there is a path straight to ground out of the 12A source, does this casue no current to flow else where in the circuit?

Hiii! This is a multi-element winding diagram with its tracing. I want to ask if what I did was right? Because I only self-studied with the handouts given by my instructor, he didn't give us specific information regarding winding diagrams, only general knowledge about them. I've been researching for days to know if what I'm doing is right, but I can't find any that is relevant. Hope you can help me. T.T